Samsung Unveils HBM5 and zHBM AI Memory Roadmap

Samsung Electronics unveiled a multi-phase roadmap for high-bandwidth memory (HBM) during Hot Chips 2026 and the Memory Executive Summit in Taipei. The company introduced the CUBE strategy—focusing on Capacity, Utilization, Bandwidth, and Efficiency—to guide AI memory design and overcome the limits of planar scaling through 3D vertical integration.

A central component of the plan is HBM5, targeted for volume production around 2028. Samsung aims for HBM5 to deliver twice the overall performance of HBM4E with a 20% improvement in performance per watt, utilizing an in-house 2nm logic process for its base dies.

For longer-term development, the company detailed zHBM, a zero-distance architecture that stacks DRAM directly on top of the processor. By eliminating the silicon interposer, Samsung expects to increase performance eightfold over HBM4E and potentially reduce I/O power by 70%, with a projected launch after 2029. Additionally, the company announced zNAND-O, a high-capacity NAND flash product designed for large language models, with customer sampling expected in 2028.