IBM Unveils First Sub-1 Nanometer Chip Technology

On June 25, 2026, IBM unveiled the world's first sub-1 nanometer semiconductor technology, operating at a 0.7 nanometer (7 angstrom) process node. Developed at a research facility in Albany, New York, the breakthrough utilizes a three-dimensional architecture called nanostack. This design vertically stacks and staggers transistors, allowing nearly 100 billion transistors to be packed onto a chip the size of a fingernail—nearly double the density of the company's 2021 2nm chip.

IBM projects the technology will provide up to 50 percent more performance or 70 percent greater energy efficiency, specifically targeting the needs of generative AI and cloud infrastructure. The company collaborated with industry partners including ASML, Lam Research, Tokyo Electron, and SCREEN Semiconductor Solutions to develop the High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography processes required for this scaling. Alongside the chip announcement, IBM also announced plans to launch Anderon, a standalone quantum foundry.

While the company has demonstrated functional CMOS inverter operation, the technology remains a laboratory prototype. Commercial production is expected within five years, though IBM will likely license the technology to foundries rather than managing high-volume manufacturing. Industry analysis notes that the nanostack architecture achieves performance gains equivalent to theoretical features smaller than 1 nanometer.